A Current Reuse CMOS RF Front-End for 4G LTE Systems

This proposed architecture is a single-end to dual-end CMOS RF front-end which is applied for LTE system. This work use Digital IF receiver architecture including current reuse source inductive degeneration LNA and folded-cascode mixer in accord with 3GPP LTE system standard. Since LTE is a communication protocol applied on handheld devices, the demands of circuit designs are based on low power and high gain. The most important parameters of front-end circuits of receivers are Noise Figure and linearity. The central frequency of RF circuit operates between 2360 to 3010MHz including LTE stand band 7. The front-end achieves 24.032 dB conversion gain, 6.48 dB NF, -14 dBm IIP3, -23.5 dBm P1dB and 2.532 mW power consumption. All the circuits are designed in 0.18 μm CMOS process with 1.2V supply voltage.